1. Field of the Invention
The present invention relates generally to a filter circuit and is directed more particularly to a filter circuit utilizing a CTD (charge transfer device) such as a BBD (bucket brigade device).
2. Description of the Prior Art
In general, a prior art filter circuit is formed as shown in FIG. 1 in which 1 designates an input terminal which is connected to the base of a PNP transistor 2 whose collector is grounded and whose emitter is connected through a resistor 3 to a power supply terminal 4 and also through a diode 5 in the reverse direction to one end of a capacitor C0 the other end of which is connected to a clock terminal 6. The former end of the capacitor C0 is also connected to the emitter of an NPN transistor Q1. The collector of transistor Q1 is connected to the next stage via the emitter of an NPN transistor Q2 in the next stage. Similarly, the collectors and emitters of the NPN transistors Q2 to Q2n (n is a positive integer) are connected in series, and capacitors C1 to C2n are connected between the bases and collectors of the respective transistors Q1 to Q2n, respectively. The capacitance values of the capacitors C1 to C2n are all equal to that of the capacitor C0 so that all have the value C, and the bases of the odd-numbered transistors Q1, Q3, . . . Q.sub.2n-1 are connected through a clock terminal 7 to a clocking signal drive circuit 8, while the bases of the remaining, even-numbered transistors Q2, Q4, . . . Q2n are connected through the clock terminal 6 to the clocking signal drive circuit 8.
The clock terminals 6 and 7 are supplied with clock signals .phi.1 and .phi.2 which have the potentials or levels of V.sub.DC and V.sub.DC +V.sub.P, and which have a duty ratio of 50% and are opposite in polarity, as shown in FIGS. 2A and 2B. The voltage V.sub.P is selected to satisfy the following condition (1) for a voltage V.sub.CC applied to the power supply terminal 4: EQU V.sub.CC &gt;V.sub.DC +2V.sub.P ( 1)
Further, a voltage V.sub.S of an input signal applied to the input terminal 1 is selected to satisfy the following condition (2): EQU V.sub.DC +V.sub.P .ltoreq.V.sub.S .ltoreq.V.sub.DC +2V.sub.P ( 2)
In the above prior art filter circuit, the capacitors C0 to C2n are all initially charged up to the voltage V.sub.P. Further, if the voltage V.sub.S of the input signal is considered to be a DC component V.sub.SDC and an AC compound V.sub.SAC, only the AC component V.sub.SAC is initially zero. Accordingly, at the onset, the voltage at the hot-end sides of the even-numbered capacitors C0, C2, . . . C2n rises with the clock signal .phi.1 (FIG. 2A) momentarily to V.sub.DC +2V.sub.P and thereafter falls to V.sub.SDC ; then, as the clock signal .phi.1 falls, the voltage at the hot-end side of the even-numbered capacitors falls momentarily to V.sub.SDC -V.sub.P and then rises to V.sub.DC +V.sub.P as shown in FIG. 2C. The voltage at the hot-end sides of the odd number capacitors C1, C3, . . . C2n-1, falls with the clock signal .phi.2 (FIG. 2B) to V.sub.SDC -V.sub.P momentarily and then rises to V.sub.DC +V.sub.P ; then as the clock signal .phi.2 rises, the voltage at the hot-end of the odd-numbered capacitors rises momentarily to V.sub.DC +2V.sub.P and then falls to V.sub.SDC as shown in FIG. 2D.
Immediately after the input signal is applied, during high voltage portion of the first clock signal .phi.1, if the voltage V.sub.S of the input signal is taken initially as V.sub.S1 (so that V.sub.S =V.sub.S1), the potential at the hot-end side of the capacitor C0 rises to V.sub.DC +2V.sub.P and then falls to V.sub.S1, that is, the capacitor C0 becomes discharged and stores the charge of {V.sub.S1 -(V.sub.DC +V.sub.P)}C. At this time, since the transistor Q1 is OFF, no change occurs in the capacitors C1, C2, . . . C2n.
During the time that the clock signal .phi.2 has the value V.sub.DC +V.sub.P the potential of the clock signal .phi.1 becomes V.sub.DC, so that the potential at the hot-end side of the capacitor C0 becomes V.sub.S1 -(V.sub.DC +V.sub.P)+V.sub.DC =V.sub.S1 -V.sub.P. Since the transistor Q1 is biased ON, the potential at the hot-end side of the capacitor C0 increases eventually to the base potential (V.sub.DC +V.sub.P) of the transistor Q1. At this time, since the transistor Q1 operates in its active region, i.e., below the region of saturation of emitter current, the capacitor C0 is charged up through the path of the terminal 7, capacitor C1, the collector-emitter path of the transistor Q1 and capacitor C0. Since the voltage at the hot-end side of the capacitor C0 changes from V.sub.S1 -V.sub.P to V.sub.DC +V.sub.P, the charge transfer from the hot-end side of the capacitor C1 to the hot-end side of the capacitor C0 is expressed by the following equation (3): EQU {(V.sub.DC +V.sub.P)-(V.sub.S1 -V.sub.P)}C=(V.sub.DC +2V.sub.P -V.sub.S1)C (3)
As the charge of V.sub.P .multidot.C is initially stored in the capacitor C1, its final amount of charge is given as follows: EQU V.sub.P .multidot.C-(V.sub.DC +2V.sub.P -V.sub.S1)C={V.sub.S1 -(V.sub.DC +V.sub.P)}C (4)
That is, during the time that clock signal .phi.1 has the potential, V.sub.DC +V.sub.P the voltage of the capacitor C0 is V.sub.S1 -(V.sub.DC +V.sub.P), but this voltage is transferred to the capacitor C1 during the time that clock signal .phi.2 has the potential V.sub.DC +V.sub.P, so that the voltage of the capacitor C0 returns to V.sub.DC +V.sub.P. At this time, since the transistor Q2 is OFF, the voltage appearing at the hot-end side of capacitors C2, C3, . . . C2n are not changed.
Further, during the time that clock signal .phi.1 has the potential V.sub.DC +V.sub.P, if the voltage V.sub.S of the input signal is V.sub.S2 (so that V.sub.S =V.sub.S2), the capacitor C0 is charged up to V.sub.S2 -(V.sub.DC +V.sub.P), the capacitor C1 is returned to V.sub.DC +V.sub.P and the capacitor C2 is charged up to V.sub.S1 -(V.sub.DC +V.sub.P). Since the Q3 is biased OFF, the capacitors C3, . . . C2n are not changed. The above operation recurs continuously and the signal is transferred from the left to right of the sheet of FIG. 1 in synchronism with the clock signals .phi.1 and .phi.2.
When a transversal filter of, for example, a cyclic type, includes the above device, a plurality of mid taps are provided, signals with different delay times are derived therethrough, the signals are weighted with a predetermined value while being added successively, and the added signals are fed back to a predetermined portion of the preceding or former stage. Such a prior art transversal filter operates as follows.
As shown in FIG. 1, the hot-end sides of the capacitors C4, C6 and C8, from which signals are derived, are connected to emitter follower circuits 91, 92, and 93, respectively. The output signals from the emitter follower circuits 91, 92, and 93 are supplied through weighting circuits 94, 95, and 96 to an analog adding circuit 97 which supplies an added signal to a sampling hold circuit 98. The output side of the sampling hold circuit 98 is connected to the hot-end side of the capacitor C2 in the former stage.
According to the circuit of FIG. 1, the signals from the mid taps are delivered through the emitter follower circuits as voltages, the voltages are weighted at desired values and then the weighted voltages are added in an analog fashion. The added signal is supplied to the capacitor at the former stage as the charge to be fed back.
In the prior art circuit of FIG. 1, the outputs from the capacitors are derived through emitter follower circuits, and the collector-base capacitance C.sub.CB of such emitter follower circuits adversely affects their base currents I.sub.B, so that the effective pulse height of the clock signal is reduced, transfer efficency is deteriorated and the dynamic range of the signal is lowered.
Further, in the prior art, an analog adding circuit and an analog sampling hold circuit are used, so that many elements are required, a great deal of electric power is consumed, and the cost of constructing the circuit becomes high.
Further, a spike current flows through the emitter follower circuit, analog adding circuit and sampling hold circuit, and this spike current adversely affects the other circuits through the power source and ground.
In addition, it is very difficult for the DC potential at the input side of the emitter follower circuit to coincide with that at the output side of the sampling hold circuit.